Welcome to high level synthesizable VHDL project (hVHDL) documentation!


This project is under active development.

High level code example
    if ethernet_rx_is_active(ethernet_rx_ddio_data_out) then
        capture_ethernet_frame(ethernet_rx, ethernet_rx_ddio_data_out); 
    end if;

hVHDL is a set of coding patterns for standard VHDL that are designed manage complexity of digital system design in VHDL. Complexity is managed by dividing large systems into small individual pieces that can be designed, tested and updated in isolation from each other. The coding patterns allow us to support incremental design, testing and development of the VHDL source code and to increase the level of abstraction. All code has been tested with an FPGA using Xilinx Vivado, ISE, Intel Quartus or Efinix Efinity tools and simulated with GHDL.